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한국정보과학회가 선정한 SW분야 최우수학술대회에서 발표된 논문의 저자를 초청하여, 핵심연구내용 소개와 질의응답을 통해 학생들의 연구의욕을 고취하는 프로그램을 마련하였습니다. 관심 있는 분들의 많은 참여 바랍니다.

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등록자는 온라인컨퍼런스 페이지(추후 공개)를 통해 접속하실 수 있습니다.

 

Top Conference Ⅰ
6.23(수) 10:00~12:00, 온라인


좌장 : 권동업(서울대)

No.

분야

학술대회

논문제목

발표자

지도
교수

1

컴퓨터시스템

ISCA 2021

SPACE: Locality-Aware Processing in Heterogeneous Memory for Personalized Recommendations

갈홍주(연세대) 노원우

2

OSDI 2020

FVM: FPGA-assisted Virtual Device Emulation for Fast, Scalable, and Flexible Storage Virtualization

권동업(서울대)

김장우

3

DDAC 2021

DANCE: Differentiable Accelerator/Network Co-Exploration

최강현(연세대)

이진호

4

고성능컴퓨팅

HPDC 2020

Towards HPC I/O Performance Prediction through Large-scale Log Analysis

김성곤(서울대)

엄현상

5

프로그래밍언어

PLDI 2021

Alive2: Bounded Translation Validation for LLVM

이준영(서울대)

허충길

 

Top Conference Ⅱ
6.23(수) 13:00~15:00, 온라인


좌장 : 고성윤(포항공대)

No.

분야

학술대회

논문제목

발표자

지도
교수

1

스토리지

ASPLOS 2021

BCD Deduplication: Effective Memory Compression Using Partial Cache-Line Deduplication

문예빈(서울대)

안정호

2

FAST 2021

FlashNeuron: SSD-Enabled Large-Batch Training of Very Deep Neural Networks

배종현(서울대)

이재욱

3

FAST 2021

D2FQ: Device-Direct Fair Queueing for NVMe SSDs

안민우(성균관대)

정진규

4

데이터베이스

SIGMOD 2021

iTurboGraph: Scaling and Automating Incremental Graph Analytics

고성윤(포항공대)

한욱신

5

ICDE 2021

Trillion-scale Graph Processing Simulation based on Top-Down Graph Upscaling

박성우(KAIST) 김민수

6

WWW 2021

Session-aware Linear Item-Item Models for Session-based Recommendation

최민진(성균관대)

이종욱

7

고성능컴퓨팅

Eurosys 2020

An HTM-based update-side synchronization for RCU on NUMA systems

박성재(Amazon)

염헌영


Top Conference Ⅲ
6.23(수) 15:00~17:00, ICC 제주 302호&온라인


좌장 : 이우석(한양대)

No.

분야

학술대회

논문제목

발표자

지도
교수

1

컴퓨터시스템

RTSS 2020

R-TOD: Real-Time Object Detector with Minimized End-to-End Delay for Autonomous Driving

정한샘(국민대)

김종찬

2

소프트웨어공학

ASE 2020

JISET: JavaScript IR-based Semantics Extraction Toolchain

박지혁(KAIST)

류석영

3

프로그래밍언어

POPL 2021

Combining the Top-down Propagation and Bottom-up Enumeration for Inductive Program Synthesis

이우석(한양대)

이우석

4

데이터베이스

AAAI 2021

PREMERE: Meta-Reweighting via Self-Ensembling for Point-of-Interest Recommendation

김민석(KAIST)

이재길

5

WWW 2021

Learning Heterogeneous Temporal Patterns of User Preference for Timely Recommendation

조준수(포항공대)

유환조



[컴퓨터시스템]

논문제목 : SPACE: Locality-Aware Processing in Heterogeneous Memory for Personalized Recommendations

저자 : Hongju Kal, Seokmin Lee, Gun Ko, Won Woo Ro(Yonsei University)

학술대회 : ISCA 2021

발표자 : 갈홍주(연세대)

지도교수 : 노원우

논문초록 : Personalized recommendation systems have become a major AI task in modern data centers. The main challenges in processing personalized recommendation inferences are the large memory footprint and high bandwidth requirement of embedding layers. To overcome the capacity limit and bandwidth congestion of on-chip memory, near memory processing (NMP) can be a promising solution. Recent work on accelerating personalized recommendations proposes a DIMM-based NMP design to solve the bandwidth problem and increase memory capacity. Also, the performance of NMP is determined by the internal bandwidth and to address this, the prior DIMM-based approach utilizes more DIMMs to achieve higher operation throughput. However, extending the number of DIMMs could eventually lead to significant power consumption due to inefficient scaling. We propose SPACE, a novel heterogeneous memory architecture, exploiting a compute-capable 3D-stacked DRAM with DIMMs for personalized recommendations. Prior to designing the proposed system, we give a quantitative analysis of the user/item interactions and define the two localities: gather locality and reduction locality. In gather operations, we find only a small proportion of items are highly-accessed across users, and we call this gather locality. Also, we define reduction locality as the reusability of the gathered items in reduction operations. Based on the gather locality, SPACE allocates highly-accessed embedding items to the 3D-stacked DRAM to achieve the maximum bandwidth. Subsequently, by exploiting reduction locality, we utilize the remaining space of the 3D-stacked DRAM to store and reuse repeated partial sums, thereby minimizing the required elementwise reduction operations. As a result, the evaluation shows that SPACE achieves 3.2x performance improvement and 56% energy saving over the previous DIMM-based NMPs leveraging 3Dstacked DRAM with a 1/8 size of DIMMs. Also, compared to the state-of-the-art DRAM cache designs with the same NMP configuration, SPACE achieves an average 32.7% of performance improvement.

논문제목 : FVM: FPGA-assisted Virtual Device Emulation for Fast, Scalable, and Flexible Storage Virtualization

저자 : Dongup Kwon, Junehyuk Boo, Dongryeong Kim, Jangwoo Kim(Seoul National University)

학술대회 : OSDI 2020

발표자 : 권동업(서울대)

지도교수 : 김장우

논문초록 : Emerging big-data workloads with massive I/O processing require fast, scalable, and flexible storage virtualization support. Hardware-assisted virtualization can achieve reasonable performance for fast storage devices, but it comes at the expense of limited functionalities in a virtualized environment (e.g., migration, replication, caching). To restore the VM features with minimal performance degradation, recent advances propose to implement a new software-based virtualization layer by dedicating computing cores to virtual device emulation. However, due to the dedication of expensive general-purpose cores and the nature of host-driven storage device management, the proposed schemes raise the critical performance and scalability issues with the increasing number and performance of storage devices per server.
In this paper, we propose FVM, a new hardware-assisted storage virtualization mechanism to achieve high performance and scalability while maintaining the flexibility to support various VM features. The key idea is to implement (1) a storage virtualization layer on an FPGA card (FVM-engine) decoupled from the host resources and (2) a device-control method to have the card directly manage the physical storage devices. In this way, a server equipped with FVM-engine can save the invaluable host-side resources (i.e., CPU, memory bandwidth) from virtual and physical device management and utilize the decoupled FPGA resources for virtual device emulation. Our FVM-engine prototype outperforms existing storage virtualization schemes while maintaining the same flexibility and programmability as software implementations.

논문제목 : R-TOD: Real-Time Object Detector with Minimized End-to-End Delay for Autonomous Driving

저자 : Wonseok Jang, Hansaem Jeong(Kookmin University), Kyungtae Kang(Hanyang University), Nikil Dutt(University of California), Jong-Chan Kim(Kookmin University)

학술대회 : RTSS 2020

발표자 : 정한샘(국민대)

지도교수 : 김종찬

논문초록 : For realizing safe autonomous driving, the end to-end delays of real-time object detection systems should be thoroughly analyzed and minimized. However, despite recent development of neural networks with minimized inference delays, surprisingly little attention has been paid to their end-to-end delays from an object’s appearance until its detection is reported. With this motivation, this paper aims to provide more compre hensive understanding of the end-to-end delay, through which precise best- and worst-case delay predictions are formulated, and three optimization methods are implemented: (i) on-demand capture, (ii) zero-slack pipeline, and (iii) contention-free pipeline. Our experimental results show a 76% reduction in the end-to end delay of Darknet YOLO (You Only Look Once) v3 (from 1070 ms to 261 ms), thereby demonstrating the great potential of exploiting the end-to-end delay analysis for autonomous driving. Furthermore, as we only modify the system architecture and do not change the neural network architecture itself, our approach incurs no penalty on the detection accuracy.

논문제목 : DANCE: Differentiable Accelerator/Network Co-Exploration

저자 : Kanghyun Choi, Deokki Hong, Hojae Yoon(Yonsei University), Joonsang Yu(Seoul National University), Youngsok Kim, Jinho Lee(Yonsei University)

학술대회 : DAC 2021

발표자 : 최강현(연세대)

지도교수 : 이진호

논문초록 : This work presents DANCE, a differentiable approach towards the co-exploration of hardware accelerator and network ar- chitecture design. At the heart of DANCE is a differentiable evaluator network. By modeling the hardware evaluation software with a neural network, the relation between the accelerator design and the hardware metrics becomes differentiable, allowing the search to be performed with backpropagation. Compared to the naive existing approaches, our method performs co-exploration in a significantly shorter time, while achieving superior accuracy and hardware cost metrics.

[고성능컴퓨팅]

논문제목 : Towards HPC I/O Performance Prediction through Large-scale Log Analysis

저자 : Sunggon Kim(Seoul National University), Alex Sim, Kesheng Wu, Suren Byna(Berkeley), Yongseok Son(Chung-Ang University), Hyeonsang Eom(Seoul National University)

학술대회 : HPDC 2020

발표자 : 김성곤(서울대)

지도교수 : 엄현상

논문초록 : Large-scale high performance computing (HPC) systems typically consist of many thousands of CPUs and storage units, while used by hundreds to thousands of users at the same time. Applications from these large numbers of users have diverse characteristics, such as varying compute, communication, memory, and I/O intensiveness. A good understanding of the performance characteristics of each user application is important for job scheduling and resource provisioning. Among these performance characteristics, the I/O performance is difficult to predict because the I/O system software is complex, the I/O system is shared among all users, and the I/O operations also heavily rely on networking systems. To improve the prediction of the I/O performance on HPC systems, we propose to integrate information from a number of different system logs and develop a regression-based approach that dynamically selects the most relevant features from the most recent log entries, and automatically select the best regression algorithm for the prediction task. Evaluation results show that our proposed scheme can predict the I/O performance with up to 84% prediction accuracy in the case of the I/O-intensive applications using the logs from CORI supercomputer at NERSC.

논문제목 : An HTM-based update-side synchronization for RCU on NUMA systems

저자 : SeongJae Park(Amazon), Paul E. McKenney(Facebook), Laurent Dufour(IBM), Heon Y. Yeom(Seoul National University)

학술대회 : Eurosys 2020

발표자 : 박성재(Amazon)

지도교수 : 염헌영

논문초록 : Read-copy update (RCU) can provide ideal scalability for read-mostly workloads, but some believe that it provides only poor performance for updates. This belief is due to the lack of RCU-centric update synchronization mechanisms. RCU instead works with a range of update-side mechanisms, such as locking. In fact, many developers embrace simplicity by using global locking. Logging, hardware transactional memory, or fine-grained locking can provide better scalability, but each of these approaches has limitations, such as imposing overhead on readers or poor scalability on non-uniform memory access (NUMA) systems, mainly due to their lack of NUMA-aware design principles.
This paper introduces an RCU extension (RCX) that provides highly scalable RCU updates on NUMA systems while retaining RCU's read-side benefits. RCX is a software-based synchronization mechanism combining hardware transactional memory (HTM) and traditional locking based on our NUMA-aware design principles for RCU. Micro-bench-marks on a NUMA system having 144 hardware threads show RCX has up to 22.6 times better performance and up to 145 times lower HTM abort rates compared to a state-of-the-art RCU/HTM combination. To demonstrate the effectiveness and applicability of RCX, we have applied RCX to parallelize some of the Linux kernel memory management system and an in-memory database system. The optimized kernel and the database show up to 24 and 17 times better performance compared to the original version, respectively.

[소프트웨어공학]

논문제목 : JISET: JavaScript IR-based Semantics Extraction Toolchain

저자 : Jihyeok Park, Jihee Park, Seungmin An, Sukyoung Ryu(KAIST)

학술대회 : ASE 2020

발표자 : 박지혁(KAIST)

지도교수 : 류석영

논문초록 : JavaScript was initially designed for client-side programming in web browsers, but its engine is now embedded in various kinds of host software. Despite the popularity, since the JavaScript semantics is complex especially due to its dynamic nature, understanding and reasoning about JavaScript programs are challenging tasks. Thus, researchers have proposed several attempts to define the formal semantics of JavaScript based on ECMAScript, the official JavaScript specification. However, the existing approaches are manual, labor- intensive, and error-prone and all of their formal semantics target ECMAScript 5.1 (ES5.1, 2011) or its former versions. Therefore, they are not suitable for understanding modern JavaScript language features introduced since ECMAScript 6 (ES6, 2015). Moreover, ECMAScript has been annually updated since ES6, which already made five releases after ES5.1.
To alleviate the problem, we propose JISET, a JavaScript IR-based Semantics Extraction Toolchain. It is the first tool that automatically synthesizes parsers and AST-IR translators directly from a given lan- guage specification, ECMAScript. For syntax, we develop a parser generation technique with lookahead parsing for BNFES, a variant of the extended BNF used in ECMAScript. For semantics, JISET synthesizes AST-IR translators using forward compatible rule-based compilation. Compile rules describe how to convert each step of ab- stract algorithms written in a structured natural language into IRES, an Intermediate Representation that we designed for ECMAScript. For the four most recent ECMAScript versions, JISET automatically synthesized parsers for all versions, and compiled 95.03% of the algorithm steps on average. After we complete the missing parts manually, the extracted core semantics of the latest ECMAScript (ES10, 2019) passed all 18,064 applicable tests. Using this first formal semantics of modern JavaScript, we found nine specification errors in ES10, which were all confirmed by the Ecma Technical Commit- tee 39. Furthermore, we showed that JISET is forward compatible by applying it to nine feature proposals ready for inclusion in the next ECMAScript, which let us find three errors in the BigInt proposal.

[프로그래밍언어]

논문제목 : Combining the Top-down Propagation and Bottom-up Enumeration for Inductive Program Synthesis

저자 : Lee Woosuk(Hanyang University)

학술대회 : POPL 2021

발표자 : 이우석(한양대)

지도교수 : 이우석

논문초록 : We present an effective method for scalable and general-purpose inductive program synthesis. There have been two main approaches for inductive synthesis: enumerative search, which repeatedly enumerates possible candidate programs, and the top-down propagation (TDP), which recursively decomposes a given large synthesis problem into smaller subproblems. Enumerative search is generally applicable but limited in scalability, and the TDP is efficient but only works for special grammars or applications. In this paper, we synergistically combine the two approaches. We generate small program subexpressions via enumerative search and put them together into the desired program by using the TDP. Enumerative search enables to bring the power of TDP into arbitrary grammars, and the TDP helps to overcome the limited scalability of enumerative search. We apply our approach to a standard formulation, syntax-guided synthesis (SyGuS), thereby supporting a broad class of inductive synthesis problems. We have implemented our approach in a tool called Duet and evaluate it on SyGuS benchmark problems from various domains. We show that Duet achieves significant performance gains over existing general-purpose as well as domain-specific synthesizers.

논문제목 : Alive2: Bounded Translation Validation for LLVM

저자 : Nuno P. Lopes(Microsoft Research), Juneyoung Lee, Chung-Kil Hur(Seoul National University), Zhengyang Liu, John Regehr(University of Utah)

학술대회 : PLDI 2021

발표자 : 이준영(서울대)

지도교수 : 허충길

논문초록 : We designed, implemented, and deployed Alive2: a bounded translation validation tool for the LLVM compiler’s interme- diate representation (IR). It limits resource consumption by, for example, unrolling loops up to some bound, which means there are circumstances in which it misses bugs. Alive2 is designed to avoid false alarms, is fully automatic through the use of an SMT solver, and requires no changes to LLVM. By running Alive2 over LLVM’s unit test suite, we discovered and reported 47 new bugs, 28 of which have been fixed already. Moreover, our work has led to eight patches to the LLVM Language Reference-the definitive description of the semantics of its IR-and we have participated in numerous discussions with the goal of clarifying ambiguities and fixing errors in these semantics. Alive2 is open source and we also made it available on the web, where it has active users from the LLVM community.

[스토리지]

논문제목 : BCD Deduplication: Effective Memory Compression Using Partial Cache-Line Deduplication

저자 : Sungbo Park(Intel), Ingab Kang(University of Michigan), Yaebin Moon, Jung Ho Ahn(Seoul National University), G. Edward Suh (Cornell University)

학술대회 : ASPLOS 2021

발표자 : 문예빈(서울대)

지도교수 : 안정호

논문초록 : In this paper, we identify new partial data redundancy among multiple cache lines that are not exploited by traditional memory compression or memory deduplication. We propose Base and Compressed Difference (BCD) deduplication that effectively utilizes the partial matches among cache lines through a novel combination of compression and deduplication to increase the effective capacity of main memory. Experimental results show that BCD achieves the average compression ratio of 1.94× for SPEC2017, DaCapo, TPC-DS, and TPC-H, which is 48.4% higher than the best prior work. We also present an efficient implementation of BCD in a modern memory hierarchy, which compresses data in both the last-level cache (LLC) and main memory with modest area overhead. Even with additional meta-data accesses and compression/deduplication operations, cycle-level simulations show that BCD improves the performance of the SPEC2017 benchmarks by 2.7% on average because it increases the effective capacity of the LLC. Overall, the results show that BCD can significantly increase the capacity of main memory with little performance overhead.

논문제목 : FlashNeuron: SSD-Enabled Large-Batch Training of Very Deep Neural Networks

저자 : Jonghyun Bae(Seoul National University), Jongsung Lee(Seoul National University and Samsung Electronics), Yunho Jin, Sam Son(Seoul National University), Shine Kim(Seoul National University and Samsung Electronics), Hakbeom Jang(Samsung Electronics), Tae Jun Ham, Jae W. Lee(Seoul National University)

학술대회 : FAST 2021

발표자 : 배종현(서울대)

지도교수 : 이재욱

논문초록 : Deep neural networks (DNNs) are widely used in various AI application domains such as computer vision, natural language processing, autonomous driving, and bioinformatics. As DNNs continue to get wider and deeper to improve accuracy, the limited DRAM capacity of a training platform like GPU often becomes the limiting factor on the size of DNNs and batch size-called memory capacity wall. Since increasing the batch size is a popular technique to improve hardware utilization, this can yield a suboptimal training throughput. Recent proposals address this problem by offloading some of the intermediate data (e.g., feature maps) to the host memory. However, they fail to provide robust performance as the training process on a GPU contends with applications running on a CPU for memory bandwidth and capacity. Thus, we propose FlashNeuron, the first DNN training system using an NVMe SSD as a backing store. To fully utilize the limited SSD write bandwidth, FlashNeuron introduces an offloading scheduler, which selectively offloads a set of intermediate data to the SSD in a compressed format without increasing DNN evaluation time. FlashNeuron causes minimal interference to CPU processes as the GPU and the SSD directly communicate for data transfers. Our evaluation of FlashNeuron with four state-of-the-art DNNs shows that FlashNeuron can increase the batch size by a factor of 12.4x to 14.0x over the maximum allowable batch size on NVIDIA Tesla V100 GPU with 16GB DRAM. By employing a larger batch size, FlashNeuron also improves the training throughput by up to 37.8% (with an average of 30.3%) over the baseline using GPU memory only, while minimally disturbing applications running on CPU.

논문제목 : D2FQ: Device-Direct Fair Queueing for NVMe SSDs

저자 : Jiwon Woo, Minwoo Ahn, Gyusun Lee, Jinkyu Jeong(Sungkyunkwan University)

학술대회 : FAST 2021

발표자 : 안민우(성균관대)

지도교수 : 정진규

논문초록 : With modern high-performance SSDs that can handle parallel I/O requests from multiple tenants, fair sharing of block I/O is an essential requirement for performance isolation. Typical block I/O schedulers take three steps (submit-arbitrate-dispatch) to transfer an I/O request to a device, and the three steps incur high overheads in terms of CPU utilization, scalability and block I/O performance. This motivates us to offload the I/O scheduling function to a device. If so, the three steps can be reduced to one step (submit=dispatch), thereby saving CPU cycles and improving the I/O performance.
To this end, we propose D2FQ, a fair-queueing I/O scheduler that exploits the NVMe weighted round-robin (WRR) arbitration, a device-side I/O scheduling feature. D2FQ abstracts the three classes of command queues in WRR as three queues with different I/O processing speeds. Then, for every I/O submission D2FQ selects and dispatches an I/O request to one of three queues immediately while satisfying fairness. This avoids time-consuming I/O scheduling operations, thereby saving CPU cycles and improving the block I/O performance. The prototype is implemented in the Linux kernel and evaluated with various workloads. With synthetic workloads, D2FQ provides fairness while saving CPU cycles by up to 45% as compared to MQFQ, a state-of-the-art fair queueing I/O scheduler.

[데이터베이스]

논문제목 : iTurboGraph: Scaling and Automating Incremental Graph Analytics

저자 : Ko, S., Lee, T., Hong, K., Lee, W., Seo, I.(POSTECH), Seo, J.(Hanyang University), Han, W.(POSTECH)

학술대회 : SIGMOD 2021

발표자 : 고성윤(포항공대)

지도교수 : 한욱신

논문초록 : With the rise of streaming data for dynamic graphs, large-scale graph analytics meets a new requirement of Incremental Computation because the larger the graph, the higher the cost for updating the analytics results by re-execution. A dynamic graph consists of an initial graph G and graph mutation updates ΔG of edge insertions or deletions. Given a query Q, its results Q(G), and updates for ΔG to G, incremental graph analytics computes updates ΔQ such that Q(G ∪ ΔG) = Q(G) ∪ ΔQ where ∪ is a union operator. In this paper, we consider the problem of large-scale incremental neighbor-centric graph analytics (NGA). We solve the limitations of previous systems: lack of usability due to the difficulties in programming incremental algorithms for NGA and limited scalability and efficiency due to the overheads in maintaining intermediate results for graph traversals in NGA. First, we propose a domainspecific language, L_NGA, and develop its compiler for intuitive programming of NGA, automatic query incrementalization, and query optimizations. Second, we define Graph Streaming Algebra as a theoretical foundation for scalable processing of incremental NGA. We introduce a concept of Nested Graph Windows and model graph traversals as the generation of walk streams. Lastly, we present a system iTurboGraph, which efficiently processes incremental NGA for large graphs. Comprehensive experiments show that it effectively avoids costly re-executions and efficiently updates the analytics results with reduced IO and computations.

논문제목 : PREMERE: Meta-Reweighting via Self-Ensembling for Point-of-Interest Recommendation

저자 : Minseok Kim, Hwanjun Song, Doyoung Kim, Kijung Shin, Jae-Gil Lee(KAIST)

학술대회 : AAAI 2021

발표자 : 김민석(KAIST)

지도교수 : 이재길

논문초록 : Point-of-interest (POI) recommendation has become an important research topic in these days. The user check-in history used as the input to POI recommendation is very imbalanced and noisy because of sparse and missing check-ins. Although sample reweighting is commonly adopted for addressing this challenge with the input data, its fixed weighting scheme is often inappropriate to deal with different characteristics of users or POIs. Thus, in this paper, we propose PREMERE, an adaptive weighting scheme based on meta-learning. Because meta-data is typically required by meta-learning but is inherently hard to obtain in POI recommendation, we self-generate the meta-data via self-ensembling. Furthermore, the meta-model architecture is extended to deal with the scarcity of check-ins. Thorough experiments show that replacing a weighting scheme with PREMERE boosts the performance of the state-of-the-art recommender algorithms by 2.36-26.9% on three benchmark datasets.

논문제목 : Trillion-scale Graph Processing Simulation based on Top-Down Graph Upscaling

저자 : Himchan Park(KAIST), Jinjun Xiong(IBM Thomas J. Watson Research Center), Min-Soo Kim(KAIST)

학술대회 : ICDE 2021

발표자 : 박성우(KAIST)

지도교수 : 김민수

논문초록 : As the number of graph applications increases rapidly in many domains, new graph algorithms (or queries) have become more important than ever before. The current twostep approach to develop and test a graph algorithm is very expensive for trillion-scale graphs required in many industrial applications. In this paper, we propose a concept of graph processing simulation, a single-step approach that generates a graph and processes a graph algorithm simultaneously. It consists of a top-down graph upscaling method called V-Upscaler and a graph processing simulation method following the vertex-centric GAS model called T-GPS. Users can develop a graph algorithm and check its correctness and performance conveniently and costefficiently even for trillion-scale graphs. Through extensive experiments, we have demonstrated that our single-step approach of V-Upscaler and T-GPS significantly outperforms the conventional two-step approach, although ours uses only a single machine, while the conventional one uses a cluster of eleven machines.

논문제목 : Learning Heterogeneous Temporal Patterns of User Preference for Timely Recommendation

저자 : Junsu Cho, Dongmin Hyun, SeongKu Kang, Hwanjo Yu(POSTECH)

학술대회 : WWW 2021

발표자 : 조준수(포항공대)

지도교수 : 유환조

논문초록 : Recommender systems have achieved great success in modeling user’s preferences on items and predicting the next item the user would consume. Recently, there have been many efforts to utilize time information of users’ interactions with items to capture inherent temporal patterns of user behaviors and offer timely recommendations at a given time. Existing studies regard the time information as a single type of feature and focus on how to associate it with user preferences on items. However, we argue they are insufficient for fully learning the time information because the temporal patterns of user preference are usually heterogeneous. A user’s preference for a particular item may 1) increase periodically or 2) evolve over time under the influence of significant recent events, and each of these two kinds of temporal pattern appears with some unique characteristics. In this paper, we first define the unique characteristics of the two kinds of temporal pattern of user preference that should be considered in time-aware recommender systems. Then we propose a novel recommender system for timely recommendations, called TimelyRec, which jointly learns the heterogeneous temporal patterns of user preference considering all of the defined characteristics. In TimelyRec, a cascade of two encoders captures the temporal patterns of user preference using a proposed attention module for each encoder. Moreover, we introduce an evaluation scenario that evaluates the performance on predicting an interesting item and when to recommend the item simultaneously in top-K recommendation (i.e., item-timing recommendation). Our extensive experiments on a scenario for item recommendation and the proposed scenario for item-timing recommendation on realworld datasets demonstrate the superiority of TimelyRec and the proposed attention modules.

논문제목 : Session-aware Linear Item-Item Models for Session-based Recommendation

저자 : Minjin Choi, Jinhong Kim(Sungkyunkwan University), Joonseok Lee(Google Research, Seoul National University), Hyunjung Shim(Yonsei University), Jongwuk Lee(Sungkyunkwan University)

학술대회 : WWW 2021

발표자 : 최민진(성균관대)

지도교수 : 이종욱

논문초록 : Session-based recommendation aims at predicting the next item given a sequence of previous items consumed in the session, e.g., on e-commerce or multimedia streaming services. Specifically, session data exhibits some unique characteristics, i.e., session consistency and sequential dependency over items within the session, repeated item consumption, and session timeliness. In this paper, we propose simple-yet-effective linear models for considering the holistic aspects of the sessions. The comprehensive nature of our models helps improve the quality of session-based recommendation. More importantly, it provides a generalized framework for reflecting different perspectives of session data. Furthermore, since our models can be solved by closed-form solutions, they are highly scalable. Experimental results demonstrate that the proposed linear models show competitive or state-of-the-art performance in various metrics on several real-world datasets.


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